2.2 Memory system

The memory of most computer consists of multiple memory chips. In the most simplistic case, we can assume all memory chips are the same size. Interestingly, the address pins of all memory chips are tied. This means that pin A0 (bit 0 of address) of all memory chips are connected electrically. Pin A1 (bit 1 of address) of all memory chips are connected (but separated from A0) and so on.

This also applies to the data pins and the read/write pin.

However, the chip select pin of each memory chip is connected separately to a memory management unit (MMU). An MMU is usually integrated into a CPU, although in certain architectures, the MMU is a chip physically separated from the CPU.

One function of the MMU is to figure out which memory chip should be used based on an address. Let us consider the following example:

• each memory chip has 2⁹ = 512 locations
• each location is a byte wide
• the system has 8 such memory chips, numbered chip 0 to chip 7.
• CS0 (chip select 0) connects from the MMU to the chip select of memory chip 0, and so on

From the hardware standpoint, there is a total of 8 × 512 = 4096 bytes. This means that in software, an instruction should be able to address any one of the 4096 locations. The memory space has byte location 0 to byte location 4095.

If an instruction wants to access location x, how should the MMU decide which chip to use (and hence which chip select to assert)?

This is rather simple because of all the assumptions. ⌊⌋ is “the floor of x divided by 512”. This formula computes the chip number.

Once we identify the chip number, we have to determine the address of location on the chip to access. Due to our assumption, this is also easy to compute. The address to access on the chip is x mod512. The binary reprsentation of this value is specified on A0 to A9 (the address lines).