An I/O device operates asynchronous to the processor. This means that the processor has no idea when an I/O device will need attention, and an I/O device has no idea when the processor will be ready to service it. In fact, the I/O device has no idea where in the entire memory the processor may be executing when an interrupt occurs.
An I/O device needs attention under many conditions. The following is an example:
Note that “transmit” and “receive” applies to a variety of devices, including (but not limited to) serial ports, SATA, SCSI, USB, NIC, sound cards, keyboards, and other devices.
Some architectures have multiple interrupt lines, even multiple interrupt lines from the same device. In this case, an interrupt control (as a component of a processor) prioritizes based on an enumeration of the interrupts to determine which interrupt vector to use (and hence which source of interrupts to handle) first.
As an ISR executes, the source of the corresponding interrupt should be cleared. For example, if the source is that the receive buffer is full, then reading the receive data register clears the corresponding interrupt.