3.1 Processor side

In order to utilize interrupts, a processor must be interruptable first. Most processors, including really old ones, are interruptable. This means that there is at least one pin on the processor that is marked INT or something to the same effect.

Furthermore, a processor must have a way to enable the interpretation of the interrupt pin, and another way to disable the interruptation of the interrupt pin.

Once enabled, an assertion of the INT pin causes a series of events on the processor side:

1.
The instruction in execution (that can be anywhere in the entire memory space) gets to finish. In other words, instructions are atomic with respect to interrupts. An interrupt cannot occur in the middle of an instruction.
2.
As soon as the instruction is finished, the address of the following instruction is saved on the stack. Interrupt is disabled to prevent “stacked” interrupts.
3.
The processor looks up an address at a fixed location in memory. This is called an interrupt vector. Some processors have a table of vectors for different interrupts, and the table is indexed by an enumeration of the source of interrupts. The enumeration is usually hard wired, but sometimes programmable (like the plug-and-play hardware for PCs).
4.
The interrupt vector is an address to continue execution. The processor continues execution at this location. This location is the beginning of an interrupt service routine (ISR).
5.
An ISR should be very short, but sufficient to clear the source of the interrupt. During the course of an ISR, the INT should be cleared (de-asserted).
6.
When the ISR is done, a special return instruction pops the location earlier saved on the stack, and continues execution there. This special return instruction also reenable interrupts.

In other words, when the INT line is asserted, it is as if the hardware indirectly calls the ISR to handle the interrupt. When the ISR is finished, it returns to continue execution where an instruction was interrupted.