Why do we want to design RISC processors? After all, some single CISC instructions (in combination with operands) expands to multiple RISC instructions. Isn’t this slower?
Because of the fewer addressing modes and instructions, RISC processors require fewer gates compared to a comparable CISC processor. This means that if both are without optimization and other speed enhancing techniques, a RISC processor core is much smaller than that of a comparable CISC processor due to the reduction of transistors.
There are two immediate advantages. First, a RISC processor core is less expensive to manufacture because its surface area is smaller. More RISC processor cores can fit on a silicon wafer than a comparable CISC processor. Second, a RISC processor consumes less power because the number of transistors is reduced.
But what about processing speed? It is true that a CISC core is usually slightly faster than a comparable RISC core when instructions are examined locally. In other words, one can easily argue that since a CISC instruction like this requires n RISC instructions to accomplish the same thing, the total CPU cycles needed by a RISC core is more than the total CPU cycles needed by a CISC core.
However, this argument does not always translate to matching performance differential in real life. This is because real life performance also depends on over all code generation and compiler optimization. A RISC core that has the same size (number of transistors and area) as a CISC core usually has more registers. The increased number of registers makes it possible for a compiler to further optimize code to reuse a register whenever possible.
Even more importantly, the latest bottleneck of data centers is power. In other words, many data centers are already consuming power at the limit. This shifts the focus from performance per chip to performance per watt. Some studies have pointed out that even cell phone processors (all are RISC) have very good performance per watt ratios, and may be suitable for data center applications.