Many RISC architectures do not implement the direct addressing mode. Instead, the only addressing mode support is the indirect addressing mode.
The value of an indirect operand is the content of a memory location, and the address of the memory location is specified by one of the registers. The syntax of an indirect operand is a register (has to be a 32-bit one) enclosed in round parentheses.
For example, the following instruction initializes the byte “pointed to by eax” to zero:
Just from looking at this instruction, we cannot determine which location will be overwritten with zero. This is because the value of eax is unknown.
Recall that I said that most RISC architectures do not implement direct operands. The instruction in listing 5.3 can be implemented by the following two instructions:
The first instruction, “movl $label1, %eax”, specifies an immediate operand as the source. The source operand is simply the value of label1. label1 is defined as the address of the first location of the 32-bit integer initialized to 5. Consequently, the instruction copies the address of the integer to eax.
The second instruction, “mov $0, (%eax)” is an implied 32-bit copy. It copies the constant 0 to the 32-bit integer pointed to by eax.